The present invention relates generally to a phase-locked loop (PLL), and more particularly, to a digital to analog converter that reduces the effects of sub-threshold leakage current in a PLL.
A PLL is used to generate an oscillator signal based on an input reference signal. The oscillator signal has a phase that is directly related to the phase of the input reference signal. PLLs are widely used in modern electronic systems such as radios, telecommunication systems, computers, and so forth. In communication systems, PLLs are used to generate oscillator signals that are used for modulation and demodulation of a message signal. In electronic circuits, PLLs generate oscillator signals that are used as clock signals for synchronous operation of the circuits. To generate an oscillator signal having a predefined phase characteristic, an input reference signal and a feedback signal derived from the oscillator signal, are used. Subsequent to a time period known as the lock time, the phase of the oscillator signal locks to the phase of the input reference signal according to a predefined relationship. For example, the PLL may be programmed to generate the oscillator signal having a frequency that is an integer multiple of the frequency of the input reference signal.
In operation, a control voltage signal corresponding to the input reference signal is generated. The control voltage signal is converted to a current signal and the current signal is mirrored into a current-controlled oscillator (CCO) using current mirror circuits, such as digital-to-analog converters (DACs). The CCO generates the oscillator signal based on the mirrored current signal. This type of circuit functions satisfactorily for low frequency range PLLs. However, it fails to produce oscillator signals with satisfactory fidelity in high frequency range (>50 MHz) PLLs. Defects are introduced by sub-threshold leakage currents generated by internal transistors of the DAC when the DAC is in a non-conducting state. The current signals required for generation of low-frequency oscillator signals have small magnitudes that are comparable with the magnitudes of the sub-threshold leakage currents. Due to the comparable magnitudes of the current signals and the sub-threshold leakage currents, the leakage currents can substantially alter the magnitude of current signals provided to the CCO, causing the frequency of the oscillator signal to differ from the desired frequency, which leads to poor locking of the PLL.
The above-described problem may be overcome by designing the internal transistors to have a much greater length (L) than a minimum length allowed by the process. However, increasing the length causes an increase in the voltage headroom of the transistor, which may be reduced by increasing the transistor width (W) by a factor of 10 or more. However, the area of the transistor becomes 100 times or greater for the same voltage headroom with reduced leakage current and results in an increased silicon area and increased product cost.
Another method to overcome the problem of leakage currents is to predict the magnitude of the leakage current generated as a function of the control voltage signal. However, the absence of accurate mathematical models in less studied systems magnifies the above-described shortcoming. Additionally, the problem is exacerbated at fast corners of transistors and high temperatures.
Therefore, it would be advantageous to have a PLL with reduced effects of sub-threshold leakage current and that overcomes the above-mentioned limitations.